Technology
FinFET design, from 16 nm to 6 nm.
A TSMC direct account. Two tape-outs on 16 nm, including a full mask set; a design kit at 12 nm; authorised for 7 nm; 6 nm AI full-custom chip design for a top AI customer.
In this section
Full-custom methodology
When transistor-level design is worth it, and the nine stages of the method
Process nodes
The FinFET nodes we have designed on
Design methodology
How a design moves from specification to silicon
Glossary
Plain-language definitions of chip-design terms
Want the detail behind a design decision?
Ask an engineering question, and we will reply.